With the help of ability to imitate the biological nervous system, Spiking Neural Networks (SNNs) architectures have become popular recently. In order to benefit at the maximum level from the low power consumption, event-based structure and parallelization features of SNN, it is more potent method to implement SNN with hardware-based applications. On the other hand, Field Programmable Gate Arrays (FPGAs) which are frequently preferred in the literature for hardware solutions, are accepted as platforms with low power requirement and parallelization capabilities. For these reasons it was performed to realize a low power and efficient design by combining the capabilities of the SNN with the skills of FPGA. In the study, training was performed using the STDP learning rule on the FPGA platform with MNIST dataset. In addition, the Integrate and Fire (IF) Neuron Model, which is preferred by researchers for low resource required hardware-based applications, was used as the neuron model in the SNN architecture and design. The model was tested with IF neurons trained using the MNIST dataset with STDP. As a result of the test, the correct prediction rate of the model was determined as 92.5%. 

Keywords - SNN, STDP, FPGA, MNIST, IF Neuron

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